The present invention generally relates to the design of field effect transistors (FETS) and, more particularly, to a device with multiple metal oxide silicon (MOS) transistor structures configured to operate as dynamic threshold metal oxide silicon (DTMOS) structures, which facilitates mitigation of the operational voltage limitation associated with conventional DTMOS transistor structures.
As is known in the art, transistors such as metal oxide silicon (MOS) transistors, have been formed in isolated regions of a semiconductor body such as an epitaxial layer which was itself formed on a semiconductor, typically bulk silicon, substrate. With an n-channel MOS field effect transistor (FET), the body is of p-type conductivity and the source and drain regions are formed in the p-type conductivity body as N+ type conductivity regions. With a p-channel MOSFET, the body, or epitaxial layer, is of n-type conductivity and the source and drain regions are formed in the n-type conductivity body as P+ type conductivity regions. It has been suggested that the semiconductor body, or layer, be formed on an insulating substrate, or over an insulation layer formed in a semiconductor substrate. Such technology sometimes is referred to as Silicon-on-Insulator (SOI) technology. Silicon-on-Insulator MOS technologies have a number of advantages over bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N+ to P+ spacing and hence higher packing density due to ease of isolation; and higher xe2x80x9csoft errorxe2x80x9d upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Silicon-on-Insulator technology is characterized by the formation of a thin silicon layer for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources in drains are formed by, for example, implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor (e.g. metal) layer structure. Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). However, the floating body can introduce dynamic instabilities in the operation of such a transistor.
An SOI field effect transistor combines two separated immunity groups, generally formed by implantation, constituting the source and drain of the transistor with the general region (device body) between them covered by a thin gate insulator and a conductive gate. Typically no electrical connection is made to the channel region and therefore the body is electrically floating. Because the source and drain regions normally extend entirely through the thin silicon layer, the electrical potential of the body is governed by Kirchoffs current law, wherein the sum of the currents flowing into the body equals the sum of the currents flowing out of the body. Because the channel potential is dependent on the body voltage, the device threshold voltage varies as a function of the body voltage.
The boundaries between the channel region and the source and drain, respectively, form junctions which are normally reversed biased. Conduction in the channel region normally occurs immediately below the gate insulator in the region in which depletion can be controlled by a gate voltage. However, the junctions at the boundary of the source and drain also form a parasitic lateral bipolar transistor, which, in effect exists somewhat below the field effect transistor and may supplement desired channel current. On the other hand, the parasitic bipolar device cannot be controlled and under some bias conditions, the operation of the parasitic bipolar device may transiently dominate the operation of the field effect transistor and effectively occupy substantially the entire silicon layer at times when the channel current is not desired.
When the device is switching, the body is coupled to various terminals of the device because there are capacitances between the body and gate, body and source, and body and drain respectively. When the voltage at the various terminal changes, the body voltage changes as a function of time which in turn effects the device threshold voltage. In certain cases, this relationship may be harmful to a device (e.g., inverter). For example, when the gate of an inverter is switched on the drain is discharged (which is typically the output of the inverter)xe2x80x94thus the drain voltage falls when the gate is switched ON. Because the drain and body are capacitively coupled, when the drain voltage drops so does the body voltage. There is an inverse relationship between the body voltage and the threshold voltage. For an NMOS device, when the body voltage falls, the device threshold voltage increases. When the body voltage increases the threshold voltage decreases. Thus, the capacitive coupling between the drain and the body results in the device losing drive current as the device is being switched.
In SOI transistors there is a lack of a bulk silicon or body contact to the MOS transistor. In some devices, it is desirable to connect the p-type conductivity body in the case of an n-channel MOSFET, or the n-type conductivity body in the case of a p-channel MOSFET, to a fixed potential. This prevents various hysteresis effects associated with having the body potential xe2x80x9cfloatxe2x80x9d relative to ground. With bulk silicon MOSFETs such is relatively easy because the bottom of the bulk silicon can be easily electrically connected to a fixed potential.
SOI devices also exhibit a kink effect which originates from impact ionization. When an SOI MOSFET is operated at a relatively large drain-to-source voltage, channel electrons with sufficient energy cause impact ionization near the drain end of the channel. The generated holes build up in the body of the device, thereby raising the body potential. The increased body potential reduces the threshold voltage of the MOSFET. This increases the MOSFET current and causes the so-called xe2x80x9ckinkxe2x80x9d in SOI MOSFET current vs. voltage (I-V) curves.
With regard to the lateral bipolar action, if the impact ionization results in a large number of holes, the body bias may be raised sufficiently so that the source region to body p-n junction is forward biased. The resulting emission of minority carriers into the body causes a parasitic npn bipolar transistor between source, body and drain to turn on, leading to loss of gate control over the MOSFET current.
A solution to controlling floating body effects and threshold voltages is known as a dynamic threshold metal oxide field effect transistor (DTMOS). A large improvement over regular MOSFET can be achieved when the gate and body of the MOSFET are electrically coupled. These devices offer improvements in power consumption in addition to reduced threshold voltages and faster switching times. This advantage is enhanced for SOI devices where base current and capacitances are appreciably reduced because of very small junction areas. However, these device are limited to operation of about a diode drop 0.6-0.8 volts. If the voltage rises above a diode drop, the body to source and body to drain parasitic diodes will turn on and gate control will be lost. This can result in a very high current from source to drain, which may even result in destruction of the device.
In view of the above, it is apparent that there is a need in the art for a device which mitigates some of the negative effects mentioned above, relating to disadvantages of DTMOS SOI devices.
The present invention provides for a multiple DTMOS structure and method for making the same. The device of the present invention mitigates some of the aforementioned problems associated with DTMOS devices. The device of the present invention includes drain and source regions and lightly doped source and drain regions (LDD regions). The device also includes a heavily doped region alongside the drain and source regions and the LDD regions. The heavily doped region is shared by the multiple DTMOS structures and provides a capacitive coupling of the gate and body of the DTMOS structures. The capacitive coupling combines with the junction capacitance of the structure to form a capacitive voltage divider between the drain and body. This provides an ability to operate DTMOS structures above 0.6-0.8 volts resulting in increased switching speeds. Additionally, capacitive coupling mitigates dropping of body potential during switching by lowering the threshold voltage of the structure. Body potential and threshold potential are related-by controlling body potential,xe2x80x94dropping of body voltage during switching is mitigated, which in turn mitigates variances in the threshold voltage.
A multiple DTMOS system is formed by using a shared heavily doped region alongside abutting transistor structures. A single heavily doped region may be employed for multiple transistor structures or several heavily doped regions may be employed between abutting transistor structures. This provides a capacitive junction between the gate and body of each transistor structure resulting in improved performance of the system. Additionally, the source of one abutting device can be formed from the same doped region of the drain of the other abutting device. Sharing regions provides reduced cost in material and reduced device size and ultimately a faster device.
One aspect of the invention relates to a multiple MOSFET device structure. The structure comprises a plurality of MOSFET devices sharing at least one heavily doped region extending underneath a gate region of at least two of the plurality of MOSFET devices. The shared heavily doped region provides a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the MOSFET devices between a body region and the gate region.
Another aspect of the device relates to a multiple transistor device. The multiple transistor device comprises a plurality of transistor devices. Each of the plurality of transistor devices comprises an N+ source region and an Nxe2x88x92 lightly doped source region, an N+ drain region and an Nxe2x88x92 lightly doped drain region and a P++ heavily doped region. The P++ heavily doped region resides alongside at least a portion of one of the Nxe2x88x92 lightly doped source region and the Nxe2x88x92 lightly doped drain region of each of the plurality of transistor devices. A P+ body region resides below a gate region and between the source and drain regions of each of the plurality of transistor devices. The P++ heavily doped region provides a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the device between the body region and the gate of each of the plurality of transistor devices.
Yet another aspect of the device relates to an SOI multiple NMOS structure comprising a silicon substrate, an insulating oxide layer formed over the substrate, a top silicon layer formed over the insulating oxide layer, a plurality of gates formed over a portion of the top silicon layer, each of the plurality of gates corresponding to an NMOS structure, a gate oxide formed between the plurality of gates and the top silicon layer, N+ source and N+ drain regions formed in the top silicon layer for each of the multiple structures, Nxe2x88x92 lightly doped source and drain extension regions formed in the top silicon layer for each of the multiple structures, a P++ heavily doped region formed along the length of the top silicon layer extending beneath the plurality of gates, the P++ regions having higher dopant concentration than the N+ regions and residing alongside a portion of the respective Nxe2x88x92 regions, wherein the P++ region provide a capacitive coupling between a body region and a gate for each of the NMOS structures and form a capacitive voltage divider with the junction capacitance of each of the NMOS structures.
Another aspect of the present invention relates to a multiple DTMOS structure. The multiple DTMOS system comprises at least two abutting DTMOS structures each comprising: a source region, a drain region, a gate region and a body region, and a capacitance formed underneath the gate regions and alongside at least one of the source region and the drain region of the at least two abutting DTMOS structures.
Still another aspect of the invention relates to a method of forming a multiple MOSFET structure. The method comprises the steps of forming lightly doped regions in a substrate, forming the same number of source and drain regions as lightly doped regions in the substrate, the source and drain regions being at least partially below the corresponding lightly doped regions and at least one of the source and drain regions being shared between abutting MOSFET structures and forming a highly doped region adjacent to the lightly doped regions.
Another aspect of the present invention relates to a method of forming an SOI multiple NMOS structure, comprising the steps of using a SIMOX process to form a silicon base, an oxide layer between the base and a top silicon layer, forming Nxe2x88x92 lightly doped regions in the top silicon layer, forming the same number of N+ source and drain regions as the lightly doped regions in the top silicon layer, the source and drain regions being at least partially below a corresponding lightly doped region and forming a P++ heavily doped region extending alongside the Nxe2x88x92 lightly doped regions and the N+ source and drain regions in the top silicon layer wherein the P++ region provide a capacitive coupling between a body region and a gate of at least one of the multiple NMOS structures and forms a capacitive voltage divider with the junction capacitance of the NMOS structure.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.